The present invention relates to a data processor system and more particularly, to an arbitration circuit which is suitably used when a plurality of requesters demand one object at the same time.
This type of arbitration circuit has conventionally employed a fixed priority system or an arrival order system. Another similar system is disclosed in JP-A-3-152657.
The above patent application is directed to a multi-processor memory request control system which comprises a plurality of processors provided as spaced by different distances from a memory shared by the plurality of processors, and wherein the respective processors can have a constant access time to the memory regardless of the distances from the memory.
In this technique, a selection circuit incorporating the above arbitration circuit sequentially selects the memory requests of the processors on an alternative basis in the ascending order of distance of the processors from the memory to obtain the eventual memory request. When the selection circuit uses an arbitration system for selecting the memory requests merely in the arrival order, the memory request of the processor farther located from the memory is more often alternatively selected than the memory request of the processor less farther located, which results in that the processor located closer to the memory can make access to the memory more quickly without being awaited. In addition, the memory request of the processor located farther from the memory can arrive at the memory only after a longer time. As a result, when the above two factors are considered, the processor farther located from the memory will have a much longer access time.
In the above technique, priority information for controlling the selection order in the selection circuit is attached to the memory request and further the arbitration is carried out in the following manner.
(1) The arbitration circuit compares the non-selection memory request (which is being awaited because the buffer of a next-stage selection circuit is full) already arrived at the selection circuit with a memory request newly arrived thereat with respect to the priority information of the requests, and according to the magnitude of the priority information, selects and determines one of the memory requests to be next selected regardless of their arrival time.
(2) The priority information of the memory request is added by a predetermined value to increase the priority each time the memory request is selected at the selection circuit.
(3) The priority information of the memory request not selected through the arbitration is also added by a predetermined value to increase the priority for the next arbitration.
In this system, thus, the memory request of the processor farther located from the memory may have a higher priority as the memory request comes closer to the memory through the above operation (2) and may be selected faster than the memory request of the processor located closer to the memory through the operation (1). Further, even when a series of the memory requests are issued from the processors farther located to the memory, since the memory request of the processor located closer thereto is increased in its priority through the operation (3) each time the request fails to be selected, whereby the memory request can be selected relatively soon. In this way, the aforementioned system enables the access times of the respective processors to the memory to be made substantially constant regardless of the distances of the processors to the memory.
The arbitration method above, however, is defective in that the memory requests of two of the plurality of processors are sequentially selected on alternative basis, which undesirably requires the increase of the number of selection parts in proportion to the number of such processors, and further in that the selection parts are connected in series, which undesirably requires a long processing time resulting from the necessity of the arbitration of all the processors.